SLIM-ADC-16
Analog to Digital Converter
Updated 4-30-08.  Update page for name changes.  No pwb or schematic changes.
Updated 7-14-08.  Parts list revised for incorrect switch (SW1, SW2) part number.
Updated 8-11-09.  Add explanation for Optional Power Modification when used with MSA/VNA

SLIM-ADC-16, AtoD Converter, 16 bit, size A
Use your mouse's "right click" and "Save Link" to download the current versions:
a.
  SKSLIM-ADC-16.sch Rev 0, Schematic, in ExpressPCB software.
b.  PWB-ADC10.pcb Rev 0, Base artwork for PWB, in ExpressPCB software.  Use this drawing to order the pwb from Express, or use as Layout to locate the parts on the SLIM-ADC-16.
c.  PLSLIM-ADC-16.txt Rev A, Parts List in text format.  Open with Exel or Lotus, etc.
d. 
Download the AD7685 data sheet at: http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad7685/products/product.html

Release History
Original Release: Released 7-01-2007
Part #: SLIM-ADC-16 Rev 0, Released 7-01-2007
Schematic: SKSLIM-ADC-16 Rev 0, Released 7-01-2007
Parts List: PLSLIM-ADC-16 Rev A, Revised 7-14-2008
PWB: PWB-ADC10 Rev 0, Released 7-01-2007

    The SLIM-ADC-16 is a dual 16 bit, serial, analog to digital converter, using two AD7685's.  There is no manual adjustment to set the A to D range.  It is not needed to obtain excellent resolution in the MSA and VNA systems.  Each AtoD will digitize its input of 0 to 5 volts to a bit value of 0 to  65535 bits.  This equates to 76.3 uv per bit.
      Both A/D's will capture, and clock out their data simultaineouslyThe software commands both U2 and U3 to begin conversion with a single toggle of the signal, "CONVERT".  16 toggles of the signal, "SERCLOCK", causes the I.C. to output a serial stream of 16 bits.  The serial SDO outputs of the AtoD I.C.'s have limited (500 ua) current capability.  Therefore, the open collectors of Q1 and Q2 provide buffering and current sinking to drive the "WAIT" and "ACK" lines to the LPT port of the Computer. The Computer's LPT port is nominally a TTL compatible input with a pull up resistor to +5 volts. It can also drive a pull-up on a +3.3v bus.
    The circuit is designed with thru hole pads, to allow each input to be connected to an external switch. The switch selects the amount of capacitance to be placed in shunt with the input.  Each switch is a single pole, dual throw, with a non-connecting center position. This allows a selection of 3 different integration times (Video Bandwidth).  This module is expected to be mounted very close to the front panel of the integrated system so that the user can mount the switches on the front panel and maintain very short leads from the switches to the bottom of the module.
    The base PWB has the part number, PWB-ADC10.  The "10" signifies the use of a 10 pin MSOP package.  There are other A/D I.C.s with this package.  More A/D SLIMs could be created from this pwb design.
  For the Basic MSA, only the U2 section needs to be populated.  The U3 section is used for the VNA extension of the MSA.

Optional Power Modification to
SLIM-ADC-16 when used in the MSA with VNA extension:
  This optional modification allows the
SLIM-ADC-16 to be powered directly by the Phase Detector Module's regulated +5 volts. This causes both modules to use the same regulated +5 volts. This results in more accurate Phase Measurements with the VNA.
    The modification is quite simple: Remove and delete U1, the 78L05. Jumper a wire between the two pads that supported U1. The pads are U1 pin 3, to U1 pin 1. The power input at P1 pin 2 must be +5 volts, which is provided by the Phase Detector Module.

SKSLIM-ADC-16, Schematic of SLIM-ADC-16
slim/skslim_adc_16.gif

PWB-ADC10, Artwork for pwb, and Layout for SLIM-ADC-16
slim/pwb_adc10.gif  slim/atod.JPG

How to Control the SLIM-ADC-16
   
Two lines control this module, the CONVERT and SERCLOCK.  Both AtoD chips are controlled simultaneously. Before conversion these lines are held low. To begin Conversion, the CONVERT is commanded high. This initiates the in-chip sample and hold circuit. While CONVERT is high, any voltage changes on the analog inputs will be disregarded. Also, the SDO output will be high impedance (WAIT and ACK will be high impedance).  It now takes approximately 2 usec for the 16 bit conversion (Sample) to take place. When complete, the 16 bit data word will be stored in its buffer (Hold). After conversion is complete, the CONVERT signal is brought low. The MSB (D15) will be present on the SDO pin (its inversion is on the line back to the computer, WAIT or ACK).  Each time the SERCLOCK is brought low, the data word is shifted by one bit. The Data is valid 15 nsec after the negative edge of SERCLOCK. It takes 16 SERCLOCK's to shift out the 16 bit data word.
    If no data is clocked out of the buffer, the next
CONVERT signal will overwrite the buffer.
  The MSA Program causes this computer action:
Begins with CONVERT and SERCLOCK low.
CONVERT to high.  Initiates the A to D conversion process.
CONVERT to low. (High to low takes about 5 usec, allowing the minimum 2 usec. conversion time requirement)
SERCLOCK to high.  D15 MSB is valid on SDO, and is read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D14 bit is valid on SDO, and is read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D13 bit is valid on SDO, and is read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D12 bit is valid on SDO, and is read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D11 bit is valid on SDO, and is read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D10 bit is valid on SDO, and is read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D9 bit is valid on SDO, and is read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D8 bit is valid on SDO, and is read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D7 bit is valid on SDO, and is read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D6 bit is valid on SDO, and is read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D5 bit is valid on SDO, and is read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D4 bit is valid on SDO, and is read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D3 bit is valid on SDO, and is read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D2 bit is valid on SDO, and is read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D1 bit is valid on SDO, and is read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D0 bit is valid on SDO, and is read by computer
SERCLOCK to low.  SDO is high impedance.
Subsequent SERCLOCK's do nothing.